In order to mimic the performance of the auditory system, cochlear models have been experimented with over the last few years as front-ends in speech/music analysis and recognition systems. A principle obstacle to their wider acceptance, however, is their heavy computational cost. Consequently, hardware implementations of these models have been an attractive option to achieve real-time performance. So far, successful attempts have employed analog designs, specifically, using subthreshold and operating transconductance amplifiers to build a cascade of second-order filter stages. A second approach is to use a bank of switched-capacitor filters (SCF's). SCF's in general have extremely precise and reliable response characteristics that would obviate the need for any post-design tuning. However, several difficulties arise when implementing the cochlear filters for sound processing using switched-capacitor filters. One is the broad frequency range that stretches to relatively low frequencies. Another is the large number of channels needed. Conventional biquad designs require a capacitance spread ratio of approximately 1/(.OMEGA..sub.0 T), where .OMEGA..sub.0 is the pole frequency of the biquad and T is the sampling period. For low frequency channels, this ratio becomes very large, and VLT circuits have to be used. In the prior VLT circuit design the output signal is only valid in one phase of a bi-phasic timing period not the entire clock period, thus a sum-gain amplifier with same input phase is advantageous since no sample-and-hold circuits are required. In addition, due to a great number of cochlear channels required for real-time-applications, circuit-sharing among channels described below reduces the number of components needed to implement.
The most pertinent prior art as to the filter bank topology includes Chang et al. U.S. Pat. No. 5,182,521 entitled `Time Multiplexed Switched Capacitor Circuit Having Reduced Capacitance` whose objectives included reduced area and component requirements for voice/music applications. Significant differences of this patent and the instant disclosure includes (1) Chang et al.'s. use of multiple states for switching capacitor's versus the instant disclosure's use of only a bi-phase; (2) Chang et al.'s device is more restricted in frequency range versus the instant disclosure; (3) Chang et al's device uses conventional switched-capacitor circuits which requires more silicon area to fabricate compared to the instant disclosure; and (4) Chang et al.'s device shares capacitors versus the instant disclosure's use of the filter bank's parallel sharing of the elementary filter.
The most pertinent art as to the sum-gain amplifier design of the instant disclosure includes Temes et al's U.S. Pat. No. 4,543,534 entitled `Offset Compensated Switched Capacitor Circuits` which teaches of a sample-hold circuit requirement for the input to the circuit for addition and subtraction operation due to the different time phases used within a time period. The instant disclosure does not require a sample hold circuit to accomplish this objective since all inputs to the amplifier occur during the same time phase. In addition, area-efficient sum-gain amplifiers are designed to reduce silicon area. The instant disclosure uses a similar switching device means for a bi-phasic operating regime as taught by the Temes et al. teaching which is hereby incorporated by reference.